1. Technical Field
The present invention relates to a printed circuit board (PCB) and a method of fabricating the same.
2. Description of the Related Art
Recently, in order to cope with an increase both in signal transmission speed and density of a semiconductor chip, the demand for techniques for directly mounting a semiconductor chip on a PCB is increasing. Thus, the development of a PCB having high density and high reliability capable of coping with the increase in the density of the semiconductor chip is required.
The requirements for the PCB having high density and high reliability are closely related to the specs of the semiconductor chip, and may include for example circuit fineness, high electrical properties, high signal transmission structure, high reliability, high functionality and so on. Hence, there is a need for techniques for fabricating the PCB having a fine circuit pattern and micro via holes in accordance with such requirements.
Typically, examples of a method of forming the circuit pattern of the PCB include a subtractive process, a full additive process, and a semi-additive process. Among them, a semi-additive process enabling the fineness of the circuit pattern is currently receiving attention.
FIGS. 1 to 6 are cross-sectional views sequentially showing a process of forming the circuit pattern using a semi-additive process according to an embodiment of a conventional technique. With reference to these drawings, the method of forming the circuit pattern is described below.
As shown in FIG. 1, a via hole 16 is processed in an insulating layer 12 having a metal layer 14 formed on one surface thereof.
Next, as shown in FIG. 2, an electroless plating layer 18 is formed on both the insulating layer 12 and the inner wall of the via hole 16. The electroless plating process functions as a pretreatment procedure of a subsequent electroplating process, and the electroless plating layer 18 should be provided at a predetermined thickness or more (e.g. 1 μm or more) in order to form an electroplating layer 24.
Next, as shown in FIG. 3, a dry film 20 is placed thereon, and is then patterned to have an opening 22 for exposing a circuit pattern forming region.
Next, as shown in FIG. 4, the electroplating layer 24 is formed in both the opening 22 and the via hole 16.
Next, as shown in FIG. 5, the dry film 20 is removed.
Finally, as shown in FIG. 6, a portion of the electroless plating layer 18 on which the electroplating layer 24 is not formed is removed through flash etching, quick etching or the like, thus forming the circuit pattern 28 including a via 26.
However, because the circuit pattern 28 resulting from the conventional semi-additive process is provided in the form of a positive pattern on the insulating layer 12, it may be undesirably separated from the insulating layer 12. In particular, as the circuit pattern 28 becomes finer, the contact area between the insulating layer 12 and the circuit pattern 28 is reduced, thus weakening adhesivity therebetween, so that the circuit pattern 28 is easily separated. In a multilayered PCB, the separation of the circuit pattern 28 formed on the outermost layer drastically deteriorates the reliability of the PCB.
With the recent goal of overcoming the above problem, a new process is proposed. For example, there is LPP (Laser Patterning Process) including forming a trench in an insulating layer using a laser and performing plating, polishing and etching thus forming a circuit pattern.
FIGS. 7 to 10 are cross-sectional views sequentially showing a process of forming the circuit pattern using LPP according to another embodiment of a conventional technique.
First, as shown in FIG. 7, a trench 56 including a circuit pattern trench 56a and a bump pad trench 56b is processed using a laser in an insulating layer 52 having a metal layer 54 formed on one surface thereof.
Next, as shown in FIG. 8, an electroless plating layer 58 is formed on both the insulating layer 52 and the inner wall of the trench 56.
Next, as shown in FIG. 9, an electroplating layer 60 is formed on the electroless plating layer 58.
Finally, as shown in FIG. 10, portions of the electroless plating layer 58 and the electroplating layer 60, which are protruding from the upper surface of the insulating layer, are removed through etching or grinding, thus forming an embedded circuit pattern 64 having a via 62.
In the case where the PCB is fabricated using LPP, the circuit pattern 64 is embedded and thus the separation thereof may be advantageously prevented. However, in order to reduce plating deviation occurring between the region having the trench 56 and the region having no trench, an additional polishing process should be performed, and also, trench processing and polishing should be conducted in respective layers, undesirably prolonging the lead time. Furthermore, because equipment used in the formation of the trench is expensive, the fabrication cost is undesirably increased. Therefore, it is difficult to fabricate the multilayered PCB using only LPP.